Novas Adds Gate-Level Engineering Change Order Capability to Debussy
New nECO Module Addresses Gate-Level Timing, Functional Floorplanning and Repartitioning Changes
SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 10, 2001--Novas Software,
Inc., the leader in debug systems for complex chip designs, today
announced that it has developed the new nECO(TM) module that adds the
ability to perform a gate-level netlist Engineering Change Order (ECO)
within its Debussy® debug system. The nECO module greatly reduces
the time required to implement ECOs at the gate level by automating
netlist changes associated with timing closure, functional bug fixes,
floorplanning and design repartitioning.
Scott Sandler, president and CEO of Novas, noted, "The addition of
this new module to Debussy is further evidence of our long-term
commitment to provide our customers with robust design knowledge
systems that improve engineering productivity throughout the IC design
and verification process. The more we automate these critical,
time-consuming tasks, the greater the value we deliver in terms of
engineering resource and expense savings."
"Netlist changes that occur late in the design process are a fact
of life, undesirable and difficult to avoid," continued Sandler. "In
the typical ECO flow, engineers need to do a lot of tedious manual
effort -- the netlist files have to be searched for the logic affected
by the change, the files need to be edited to implement the changes up
and down the hierarchy, and the changes need to be tracked and
verified to make sure exactly what needs to change gets changed and
nothing more. This is a very time and resource intensive process that
is easily subject to errors."
Novas' nECO module greatly reduces the time required to complete
gate-level ECOs. The new tool is tightly integrated with the other
Debussy modules. Users take advantage of Debussy's sophisticated
knowledge-based debugging capabilities to completely understand
exactly what needs to change across numerous netlist files and
hierarchy boundaries. Rewiring is done graphically in the flattened
schematic view, where it is easy to see exactly what needs to change.
The nECO tool then propagates the change throughout the hierarchy,
automatically creating any new nets and ports that are required. Users
can commit the edits to the Debussy Knowledge Database(TM) (KDB) and
browse the changes throughout the hierarchy. Once they are satisfied
with the changes, the nECO module writes out a new set of Verilog
netlist files that reflect the changes, preserving file structure and
white space, making it easy to verify that only the desired changes
were made. The nECO tool also automatically generates an ECO report
for analysis and tracking.
Frank Hering, Hardware Engineering Manager at ATI Technologies,
stated, "Using the Debussy nECO module, we can readily find and
visualize the gates that require modification. Because we can actually
implement the ECO within the schematic, we are able to complete a
complex ECO much faster compared to our previous methodology. We can
also implement our ECOs with a much higher level of confidence due to
nECO's ability to automate error-prone tasks such as creating new
ports for cross-hierarchy changes and detect common mistakes such as
wired outputs and floating inputs. In addition, the minimal netlist
changes that occur as a result of using nECO make it very easy for us
to compare the files and determine what has actually been modified."
Wayne W.H. Wu, CAD director for Acer Laboratories, Inc. in Taiwan,
said "Without nECO, we could view in Debussy what we needed to change
at the gate-level, but we had to manually implement the changes by
editing dozens of files. This was a time consuming and error-prone
process that did not provide a report of what we had changed. Now, we
can just edit the schematic and let the tool automatically create the
new netlist files. Being able to fix gate-level problems late in the
design cycle with nECO is very beneficial to our overall design
process."
nECO Module Operation
The new nECO module for Debussy utilizes the following methodology
and flow to locate, isolate, create and finalize changes to the
netlist:
- Users locate all relevant logic with standard Debussy features
that employ powerful string and connectivity-driven search
techniques along with drag and drop of signals from the RTL
design.
- The resulting logic is then isolated in a flat, editable
schematic. The user has complete control over the amount of
surrounding logic displayed in the schematic, regardless of
the hierarchical structure of the netlist.
- Users then make necessary changes in the schematic by adding
or deleting cells or rewiring the logic.
- Before the user commits the changes, nECO displays a summary
with change details and potential problems for review. After
the changes are committed, they are reflected in all other
Debussy source code and schematic views.
- nECO then writes the modified design to a new netlist file or
files. The user controls the files that are written -- only
those with changes, everything under a given scope, or the
entire design. Comments documenting the changes are
automatically included.
- nECO generates a report that contains all the details of the
change. This report can be used for inspection or change
tracking.
nECO also supports a set of advanced features that satisfy certain
methodology-specific requirements. For example, users can easily
create a new copy of an existing module in order to make changes that
only affect a single instance of that module. For metal-only changes,
users can direct nECO to automatically locate the spare cells in the
netlist or provide them as a list of instances. Changes can then be
restricted based on the available spare cells. For floorplanning and
repartitioning, user can easily move cells or blocks to different
scopes. The nECO module maintains the connectivity of the design,
creating new nets and ports as needed.
Pricing and Availability
Novas' nECO module for Debussy is available now and U.S. pricing
starts at $50,000.
About Novas
Novas Software, Inc. focuses on improving the human understanding
process involved in debugging IC and system-on-chip (SoC) designs. The
company's technology and products provide designers with the ability
to shorten verification and debug cycles -- the most labor-intensive
and expensive portions of the design process. With its Debussy®,
Verilog and VHDL debug system, designers can easily locate, isolate,
and understand the causes of unexpected design behavior in half the
time of traditional solutions, thereby maximizing the efficiency of
engineering resources, significantly reducing costs and accelerating
the process of getting silicon to market. Novas has over 7,000 systems
in use at hundreds of customer sites worldwide. For more information
visit www.novas.com or send email to info@novas.com.
Note to Editors: Novas Software and Debussy are registered
trademarks and nECO and Knowledge Database are trademarks of Novas
Software, Inc. All other trademarks or registered trademarks are the
property of their respective owners.
Contact:
Novas Software
Lorie Bowlby, 408/467-7871
lorie@novas.com
or
KJ Communications
Kella Knack, 650/508-0371
Kjcomk@cs.com
